Future Intel Xeon E7 Processors Sighted
The “Ivy Bridge” revamp of Intel’s Xeon server processor line is not quite yet complete, but it is getting close.
The “Ivy Bridge-EX” Xeon E7 v2 chip for machines with four and eight sockets using Intel’s chipsets and spanning even more sockets using non-Intel chipsets, are supposed to ship to server makers by the end of the year. That is according to a roadmap that Intel put out earlier this year, when it talked a bit about its plans for server processors for 2013.
Intel never did get around to putting out a “Sandy Bridge-EX” variant of the Xeon E7 chip, and customers building systems with large number of sockets–SAP’s HANA in-memory database machines come immediately to mind–have had to do with the ten-core “Westmere-EX” Xeon E7 processors. These original Xeon E7 processors date from June 2011, and they have a buffered memory architecture that works in conjunction with Intel’s “Boxboro” 7500 series chipset to provide 512 GB of main memory per socket.
That Boxboro chipset was a big improvement for system makers because before the Xeon 7500 (code-named “Nehalem-EX” and dating from March 2010) and E7 chips were launched, the high-end Xeon chips still had a frontside bus architecture, which limited the scalability of the high-end Xeons. Server makers such as IBM and Hewlett-Packard had to create their own chipsets, often adding L4 cache as well, to scale machines beyond two sockets with efficiency.
It is not clear what goodies Intel will be adding as it moves to the “Brickland” chipset, which will be given the less-human name C602J. Intel had been thinking of converging the high-end Xeon E7 and Itanium processor sockets and chipsets, but that idea went out the window last year when it became clear that the Itanium chip was not going to get very much sales in a significantly diminished HP-UX server market and with tepid enthusiasm from the handful of other system makers that still supply Itanium-based machines. Intel’s public chip roadmap shows that the Xeon E7 v2 chips will be available in versions for two-sockets (2800), four sockets (4800), and eight sockets (8800), mirroring what was available for the original Xeon E7. HP is cooking up a chipset that will scale across sixteen sockets in its “Project Odyssey” effort.
There has been plenty of speculation about how many cores the future Xeon E7 v2 chips will have, but Intel has inadvertently confirmed it in an abstract for the International Solid State Circuits Conference being held in San Francisco. Mind you, the abstract doesn’t say much: “Ivytown: A 22nm 15-Core Enterprise Xeon Processor Family.”
Intel has a number of different internal codenames for chips. Among the server chip engineers, the Xeon E5-2600 in the Sandy Bridge generation was also known as “Jaketown” and the current Ivy Bridge Xeon E5-2600 v2 is known as “Ivytown.” It looks like this Ivytown codename is carrying over with the Xeon E7s as well, and there could be technical reasons for that. Intel will no doubt explain before the Xeon E7 v2 processors are formally launched sometime in early 2014.
The rumors are that the Brickland platform was designed to span the Ivy Bridge, “Haswell,” and “Broadwell” variants of the Xeon E7 chips. The Brickland chips are also said to support a goosed-up version of the QuickPath Interconnect that links multiple sockets together as well as the “Jordan Creek” scalable memory buffer, which will support both DDR3 and DDR4 main memory. The current “Mill Brook” memory buffer used with memory cards in Xeon E7 v1 chips is limited to DDR3 memory sticks. Presumably the Jordan Creek buffer chip, which sits on external memory cards between the on-die memory controller and the memory chips, has more bandwidth, lower latency, and other features to support the larger number of cores and main memory that feeds them.
Intel has let a few more tiny details about the Xeon E7 v2 chips out the door, and did so earlier this year at the Intel Developer Forum in Beijing:
What you can see here is that Intel is going to boost the memory capacity with the Xeon E7 v2 processors by 50 percent to match the identical increase in the core count. (An eight-socket Xeon E7 v1 machine can only support 8 TB of main memory, and the v2 machine will be able to do 12 TB.)
Intel has not explained what on earth “Run Sure Technology” is. It could be that the processor actually has sixteen cores on the die, with one of them kept in reserve as a hot spare. Having fifteen cores on a die is a very strange and unsymmetrical number, and it is less likely that Intel would put fifteen actual cores on the die and then activate only fourteen of them for workloads. Again, the symmetry is wrong. Computers like even multiples of two, not odd ones.
Whatever the Xeon E7 v2 systems have in store, one thing remains certain. Supermicro is out there on the front end, showing off its machine using the processors. Take a gander at this:
Supermicro was showing off its initial Xeon E7 v2 machine at the SC13 supercomputing conference in Denver last month. You can see the 48 2.5-inch drive bays at the front of the enclosure of the machine and the memory cards at the back of the enclosure. The four processors sit between the two. Supermicro is not saying much about this machine, but it has divulged that this SuperServer SYS-4048B-TRFT will use DDR3 memory running at 1.6 GHz and that the box will have eleven PCI-Express 3.0 slots and two 10 Gb/sec Ethernet ports.
As EnterpriseTechreports elsewhere, Oracle has also said that it will be creating a variant of its Exadata database cluster using the Xeon E7 v2 processors, which it vaguely said it would ship in 2014.
Others will no doubt start talking of their Xeon E7 v2 plans before too long – including Intel.