New Hybrid Memory Cube Spec Doubles Data Rates
When it comes to Hybrid Memory Cube (HMC), the innovative 3D technology that Micron Technology is counting on to replace standard DDR3 memory modules, all signs point to go. The memory maker began shipping the first samples of the technology to partners in September, and this week, the Hybrid Memory Cube Consortium (HMCC), the group responsible for defining an adoptable industry-wide interface, announced a new spec that could effectively double throughput over the existing HMC 1.0 specification.
The first draft of its HMC 2.0 spec is available to the consortium’s ten developer members – Altera, ARM, HP, IBM, Micron, Microsoft, Open-Silicon, Samsung, SK Hynix and Xilinx – as well as its growing base of adopter members, currently numbered at 120.
The new spec doubles the throughput of the original specification, boosting short-reach (SR) performance from 15 Gb/sec up to 30 Gb/sec over distances of up to 20 centimeters, and allowing the peak bandwidth of a single memory cube to soar to 480 GB/s. The updated spec also migrates the associated channel model from short-reach (SR) to very-short-reach (VSR) to align with existing industry nomenclature. The ultra-short-reach (USR) definition also increases performance: from 10 Gb/sec up to 15 Gb/sec.
The HMC 2.0 specification is on track to be finalized by the middle of this year, and will replace the previous specification which was finalized in April of last year. Micron partners Altera, Xilinx, and Open-Silicon have already begun leveraging the HPC 1.0 standard in product designs.
The HMC uses advanced through-silicon vias (TSVs) – vertical conduits that electrically connect a stack of individual chips – to combine high-performance logic with Micron’s DRAM. The 3D technology aims to address the memory wall, the ever-widening gap between the performance improvement rate of DRAM and processor data consumption rates.
The 2 GB samples that are currently shipping offer 160 GB/s of memory bandwidth, while using up to 70 percent less energy per bit compared to DDR3 memory. A 4 GB device, scheduled to debut in 2014, is expected to hit 320 GB/s per cube.
The company explains that by abstracting memory, HMC enables designers to spend more time leveraging HMC’s features and performance and less time navigating obtuse memory parameters. HMC also manages error correction, resiliency, refresh, and other such parameters associated with memory process variation.
“System designers are looking for new memory system designs to support increased demand for bandwidth, density, and power efficiency,” said Brian Shirley, vice president of Micron’s DRAM Solutions Group in a prepared statement. “HMC represents the new standard in memory performance; it’s the breakthrough our customers have been waiting for.”
Targeted applications for HMC include supercomputing, as well as in-memory computing and distributed databases on the enterprise side. Networking is also a natural fit as is any application that requires high-throughput and low-latency memory. Micron reports that high-speed networking vendors are on deck for the first productized version and an HPC-centric product is likely to be the next target.
Expect the extreme-scale computing crowd to be paying close attention. As Micron notes on its website, “With performance levels that break through the memory wall, Hybrid Memory Cube represents the key to extending network system performance to push through the challenges of new 100G and 400G infrastructure growth. Eventually, HMC will drive exascale CPU system performance growth for next generation HPC systems.”
Volume production of both the 2 GB and 4 GB HMC devices is on the roadmap for late 2014.